1. Field of the Invention
The present invention relates to an A/D converter for converting an analog signal into a digital signal, and more particularly to a parallel-type A/D converter.
2. Description of the Related Art
FIG. 10 is a diagram showing a structure of a conventional parallel-type A/D converter 800. This conventional A/D converter 800 is used for performing high-speed analog-digital conversion.
The conventional A/D converter 800 includes a reference voltage generator circuit 801, a differential amplifier array 802, a comparator circuit array 803, and an encoder circuit 805. The reference voltage generator circuit 801 uses a plurality of resistors R1-Rn for dividing a voltage, which is applied between terminals to which a top level reference voltage 801a and a bottom level reference voltage 801b are applied, so as to generate reference voltages VR1-VRn+1. The reference voltages VR1-VRn+1 are input to the differential amplifier array 802. The comparator circuit array 803 compares the reference voltages VR1-VRn+1 with an analog signal voltage input via an analog signal voltage input terminal 804 in a parallel manner. The encoder circuit 805 performs logic processing (conversion) on comparison results output by the comparator circuit array 803 so as to output a digital data signal having a prescribed resolution.
A conventional A/D converter, such as the A/D converter 800 having the above-described parallel structure, has an advantage of performing high-speed A/D conversion as compared to other conventional A/D converters of various types, such as integrating-types, series-parallel types, etc. However, there is a disadvantage of the conventional A/D converter in that as resolving power thereof is increased, the number of differential amplifiers and comparator circuits included in the conventional A/D converter is required to be increased, and therefore power consumption and an area occupied by the differential amplifiers and the comparator circuits are increased.
Japanese Laid-Open Patent Publication No. 4-43718 discloses another conventional A/D converter 900 which is improved so as to overcome the above-described disadvantage.
FIG. 11 is a diagram showing a structure of the improved conventional parallel-type A/D converter 900. The A/D converter 900 includes a reference voltage generator circuit 911, a differential amplifier array 912, an interpolation resistor array 916, a comparator circuit array 903, and an encoder circuit 905. In the A/D converter 900, the comparator circuit array 903 and the encoder circuit 905 have the same structure as corresponding elements of the A/D converter 800 of FIG. 10. However, the A/D converter 900 is different from the A/D converter 800 in that the number of resistors included in the reference voltage generator circuit 911 is less than the number of those included in the reference voltage generator circuit 801, the number of differential amplifiers included in the differential amplifier array 912 is less than the number of those included in the differential amplifier array 802 and the interpolation resistor array 916 is further included.
Specifically, the reference voltage generator circuit 911 uses m number of resistors R1-Rm, which is less than the number required in accordance with the resolving power of the A/D converter 900, for dividing a voltage, which is applied between terminals to which a top level reference voltage 911a and a bottom level reference voltage 911b are applied, so as to generate reference voltages VR1-VRm+1.
The differential amplifier array 912 uses m+1 differential amplifiers for amplifying voltage differences between each of the reference voltages VR1-VRm+1 and an input analog signal voltage input via an analog signal voltage input terminal 904, so as to output differential output voltages (non-inverted output voltages and inverted output voltages).
The interpolation resistor array 916 includes a plurality of resistors and divides a voltage, which is applied between terminals of two adjacent differential amplifiers to which non-inverted output voltages are applied, and a voltage, which is applied between terminals of two adjacent differential amplifiers to which inverted output voltages are applied, so as to be interpolated. Each of interpolated voltages derived from the non-inverted output voltages is compared with a corresponding one of interpolated voltages derived from the inverted output voltages by a corresponding comparator circuit included in the comparator circuit array 903. The comparison results are converted into a digital code by the encoder circuit 905 so as to output a digital data signal.
In the A/D converter 900, the voltage differences between each of the reference voltages VR1-VRm+1 and the analog signal voltage are amplified by multiplying the voltage differences by a gain of the differential amplifier array 912. Further, each comparator circuit included in the comparator circuit array 903 performs voltage comparison on corresponding output voltages of two adjacent differential amplifiers, which are interpolated by the interpolation resistor array 916, and therefore the number of differential amplifiers can be reduced to 1/x, where x is the number of interpolated bits, as compared to the case where the interpolation processing is not performed. Therefore, it is possible to reduce the power consumption and area occupied by the differential amplifiers to some extent.
A comparator circuit which can be used in both the A/D converter 800 of FIG. 10 and the A/D converter 900 of FIG. 11 is shown in FIG. 12.
FIG. 12 is a circuit diagram of a comparator circuit 850 for use in a conventional A/D converter.
The comparator circuit 850 compares voltage Vo applied to a gate of an NMOS transistor m1 with voltage Vob applied to a gate of an NMOS transistor m2.
When Vo greater than Vob, a drain current (Id1) of the NMOS transistor m1 is greater than a drain current (Id2) of the NMOS transistor m2. In this case, output voltages of the comparator circuit 850 are determined by load resistance (RL) and the drain currents (Id1 and Id2). The relationship between the determined output voltages of the comparator circuit 850 is represented by Q (=VDDxe2x88x92Id1xc2x7RL) less than QB(=VDDxe2x88x92Id2xc2x7RL).
When Vo less than Vob, the drain current (Id2) of the NMOS transistor m2 is greater than the drain current (Id1) of the NMOS transistor m1. The relationship between the output voltages of the comparator circuit 850 is represented by Q greater than QB.
However, even in the case where an A/D converter is configured so as to use the interpolation resistors for interpolating and comparing voltages amplified by the differential amplifiers in the above-described manner, the number of comparator circuits included in the A/D converter is required to comply with the requirements of the resolving power of the A/D converter. Specifically, 2nxe2x88x921 comparator circuits are required when the A/D converter outputs an n-bit digital code. Therefore, the A/D converter has a problem that as the resolving power of the A/D converter is increased, the number of comparator circuits included in the A/D converter is considerably increased, thereby increasing power consumption of the A/D converter.
One of techniques of reducing power consumption of a comparator circuit itself is known from Thomas Byunghak Cho, xe2x80x9cA 10 b, 20 Msample/s, 35 mW Pipeline A/D Converterxe2x80x9d, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 3, MARCH 1995, pp. 166-172. This publication describes that dynamic comparator circuits are used in a low-resolution A/D conversion section which is provided in each pipeline stage of a pipeline A/D converter, instead of using high-speed and highly-responsive constant current-type comparator circuits for use in a typical A/D converter. Since the dynamic comparator circuit does not require a constant current, the power consumption is considerably reduced in comparison with the case where the constant current-type comparator circuit is used.
However, there is a problem that the above-described dynamic comparator circuit can be used only in a low-resolution A/D converter, since the influence of offset on such an A/D converter is so great as to deteriorate comparison precision. Further, in order to use the dynamic comparator circuit in an A/D converter having relatively-high resolving power, error correction processing is required to be performed. Additional circuitry is required to perform the error correction processing, and the power consumption and a circuit area, which would be increased by the provision of the additional circuitry, are not negligible.
According to one aspect of the present invention, there is provided an A/D converter which includes: a reference voltage generation section for generating a plurality of reference voltages; a differential amplification section for amplifying a voltage difference between each of the plurality of reference voltages and an input signal voltage so as to generate a plurality of output voltage sets, each of the plurality of output voltage sets including complementary non-inverted and inverted output voltages; and an operating section for receiving the plurality of output voltage sets, the operating section being operated according to a clock signal, in which the operating section includes a comparison section having a threshold voltage Vtn, the comparison section includes an input transistor section to which first and second output voltage sets of the plurality of output voltage sets are input, and a positive-feedback section operating according to the clock signal, the first output voltage set includes a first non-inverted output voltage and a first inverted output voltage, and the second output voltage set includes a second non-inverted output voltage and a second inverted output voltage, the input transistor section performs a prescribed weighting calculation so as to determine the threshold voltage Vtn, and compares a difference between the first non-inverted output voltage and the first inverted output voltage with a difference between the second non-inverted output voltage and the second inverted output voltage so as to output a comparison result to the positive-feedback section, and the positive-feedback section amplifies the comparison result output by the input transistor section when the clock signal is at a prescribed level and retains the amplified comparison result while outputting the amplified comparison result as a digital signal.
In one embodiment of the invention, the A/D converter further includes an encoding section for encoding the digital signal.
In another embodiment of the invention, the A/D converter further includes a first interpolation section for interpolating the first and second non-inverting output voltages and a second interpolation section for interpolating the first and second inverted output voltages.
In still another embodiment of the invention, the A/D converter further includes an input signal voltage level detection section for detecting the input signal voltage so as to control the operating section according to a level of the input signal voltage.
In still another embodiment of the invention, the input transistor section includes a plurality of transistors and the weighting calculation is performed by changing respective sizes of the plurality of transistors.
In still another embodiment of the invention, the operating section includes 2n comparison sections, where n is an integer.
In still another embodiment of the invention, the plurality of transistors are provided so as to form respective prescribed transistor patterns, and dummy transistor patterns are provided at opposite ends of a series of the transistor patterns.
In still another embodiment of the invention, the plurality of transistors are provided so as to form respective prescribed transistor patterns, and the series of the transistor patterns is linearly-symmetrical with respect to a center line of the input transistor section.
In still another embodiment of the invention, the reference voltage generation section, the differential amplification section, and the operating section are formed on a single chip.
Another aspect of the present invention, there is provided a system which includes: a clock signal generation section for generating a clock signal having a variable frequency; and an A/D converter to which the clock signal generation section is connected, the A/D converter including: a reference voltage generation section for generating a plurality of reference voltages; a differential amplification section for amplifying a voltage difference between each of the plurality of reference voltages and an input signal voltage so as to generate a plurality of output voltage sets, each of the plurality of output voltage sets including complementary non-inverted and inverted output voltages; and an operating section for receiving the plurality of output voltage sets, the operating section being operated according to the clock signal, in which the operating section includes a comparison section having a threshold voltage Vtn, the comparison section includes an input transistor section to which first and second output voltage sets of the plurality of output voltage sets are input, and a positive-feedback section operating according to the clock signal, the first output voltage set includes a first non-inverted output voltage and a first inverted output voltage, and the second output voltage set includes a second non-inverted output voltage and a second inverted output voltage, the input transistor section performs a prescribed weighting calculation so as to determine the threshold voltage Vtn, and compares a difference between the first non-inverted output voltage and the first inverted output voltage with a difference between the second non-inverted output voltage and the second inverted output voltage so as to output a comparison result to the positive-feedback section, and the positive-feedback section amplifies the comparison result output by the input transistor section when the clock signal is at a prescribed level and retains the amplified comparison result while outputting the amplified comparison result as a digital signal.
Thus, the invention described herein makes possible the advantages of providing a high-speed and high-precision A/D converter which realizes low power consumption.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.